1. Field of the Invention
The present invention relates to a plasma display panel and, more particularly, to an AC plasma display panel having a sealing structure for isolating a discharge space from an external environment.
2. Description of the Related Art
A conventional AC plasma display panel will be described with reference to FIGS. 6 to 8. FIG. 6 is a partial perspective view illustrating a plasma display panel of triode surface discharge type known as a typical AC panel, and FIGS. 7(A) and 7(B) are a top view and a sectional view, respectively, illustrating major portions of a front panel of the plasma display panel. FIG. 8 is a sectional view illustrating major portions of the plasma display panel.
As shown, the conventional plasma display panel of triode surface discharge type includes a front panel 101 having pairs of main electrodes 111 for display discharge and a rear panel having address electrodes 121 for address discharge. A discharge gas of a xenon/neon gas mixture is filled in a discharge space defined between the front panel 101 and the rear panel 102. A sealing member 103 is provided between the front panel 101 and the rear panel 102 around a display region ES for sealing the discharge space from an external environment.
The main electrodes 111 in each pair are arranged in parallel adjacent relation on an inner surface of a glass substrate 112 of the front panel 101. One of the main electrodes 111 in each pair serves as a scan electrode for causing address discharge cooperatively with any of the address electrodes 121. The main electrodes 111 each include a transparent electrode 111a and a bus electrode 111b, and are covered with a dielectric layer 113 having a thickness of about 30 μm. A protective film 114 of MgO having a thickness of several thousands angstroms is provided on the surface of the dielectric layer 113.
The address electrodes 121 are arranged in intersecting relation to the main electrode pairs 111 on an inner surface of a glass substrate 122 of the rear panel 102, and covered with a dielectric layer 123 having a thickness of about 10 μm. Barrier ribs 124 each having a height of 150 μm are provided in a striped configuration between the address electrodes 121 on the dielectric layer 123, so that the barrier ribs 124 and the address electrodes 121 are arranged in alternating relation.
Next, an explanation will be given to how to produce the plasma display panel. For preparation of the front panel 101, the transparent electrodes 111a are first formed on the glass substrate 112 by a sputtering method. Then, Cr, Cu and Cr films are sequentially formed over the transparent electrodes 111a on the glass substrate 112, and a resist pattern is formed on the Cr, Cu and Cr films, which are in turn etched for formation of the bus electrodes 111b in association with the transparent electrodes 111a. Thus, the main electrode pairs 111 are formed. Then, SiO2 is deposited on the glass substrate 112 formed with the main electrode pairs 111 by a gas-phase method such as a CVD method for formation of the dielectric layer 113. Finally, MgO is deposited on the dielectric layer 113 by a vacuum vapor deposition method for formation of the protective film 114.
After the rear panel 102 is prepared, the front panel 101 and the rear panel 102 are combined in the following manner. A sealing glass paste is applied on the dielectric layer 113 of the front panel 101 around the display region ES by a dispenser method (this state is shown in FIGS. 7(A) and 7(B) which illustrate the front panel 101 in plan and in section, respectively). Then, the front panel 101 and the rear panel 102 are combined in opposed relation, and heat-treated. In the heat treatment, the glass paste is baked for formation of the sealing glass member 103. Thus, the discharge space is sealed (see FIG. 8).
Although the formation of the dielectric layer 113 is achieved by depositing SiO2 by the gas-phase method (e.g., the CVD method) in the aforesaid method, a ZnO-based frit glass is otherwise employed as a material for the dielectric layer 113a. In a prior art, a lead-containing frit glass (e.g., a PbO-based frit glass) is also used for the formation of the dielectric layer 113, but the lead-containing frit glass has recently become obsolete from the viewpoint of environmental issues and recycling.
When the bus electrodes 111b are formed in association with the transparent electrodes 111a by sequentially forming the Cr, Cu and Cr films over the transparent electrodes 111a on the glass substrate 112 of the front panel 101, forming a resist pattern on the Cr, Cu and Cr films, and etching the Cr, Cu and Cr films in the production of the conventional AC plasma display panel having the aforesaid construction, the bus electrodes 111b are liable to overhang. This makes it impossible to properly cover the bus electrodes 111b with the dielectric layer 113 formed by the gas-phase method (e.g., the CVD method). Hence, there is a possibility that voids are present on opposite sides of the bus electrodes 111b. If the front panel 101 is prepared by forming the protective film 114 on the dielectric layer 113 with the voids present on the opposite sides of the bus electrodes 111b and the plasma display panel is produced by combining the thus prepared front panel 101 and the rear plate 102, sealing the front panel 101 and the rear panel 102 by the sealing glass member 103 and filling the discharge gas in the discharge space, the discharge space is likely to communicate with the outside of the panel through the voids present on the opposite sides of the bus electrodes 111b. Therefore, the discharge space cannot be kept gas-tightly sealed. Further, where the dielectric layer 113 is formed of a PbO-free frit glass, the adhesion between the dielectric layer 113 and the bus electrodes 111b is poor. Therefore, voids are likely to be present between the dielectric layer 113 and the bus electrodes 111b. 